A Review on System Level Behavioral Modeling and Post Simulation of Built- in-Self-Test of Sigma-Delta Modulator Analog-to-Digital Converter

This paper reported extensive study and research proposal of Post simulation and behavioral modeling of Second Order sigma-delta modulator BIST technique in which include non-ideality factor such as offset error and clock jitters. For the test of the digital parts, BIST techniques have been developed and are broadly implemented in current chips. BIST technique not only avoids depending on the off-chip automatic test equipment (ATE) and reduces the test cost but increases the controllability and observability of the circuit under test also that improves the fault coverage. Proposed work focus on implementation challenges of the BIST approach for the oversampling ADC circuit and demonstrate how to achieve high-precision on-chip analog stimuli by smaller hardware cost. KeywordsBIST of Sigma-Delta Modulator ADC; Flow Diagram. __________________________________________________*****_________________________________________________